A Novel High Speed Serial Interface in UTMI+ Transceivers for USB 2.0 Hub Repeater Operations: A Proposal

By Sathish Kumar Ganesan.

Published by The International Journal of Designed Objects

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Article: Electronic $US5.00

This paper proposes a novel high speed serial interface in UTMI+ transceiver for USB 2.0 hub repeater operations, so that USB 2.0 hubs can also be supported using the UTMI+ transceivers. The UTMI+ specification is an industry standard which is used to specify an interface to which USB 2.0 ASIC, ASSP, discrete phy, system peripherals, and IP vendors can develop USB 2.0 products. It is the industry standard interface between the USB MAC (host/device/hub) and USB PHY. UTMI+ interface supports 4 levels, namely level 0 to level 3. Each level supports corresponding USB products. However, this specification does not support USB 2.0 hub products, as it cannot comply with the USB 2.0 hub repeater latency requirements, as per table 7–11 of USB 2.0 specification. Hence USB 2.0 hub developers cannot use this industry standard interface for their development, and therefore are forced to use a proprietary/non-standard interface between the USB MAC (hub) and USB PHY (upstream and downstream ports). This issue limits the UTMI+ specification, and thereby the UTMI+ transceiver cannot be reused for USB 2.0 hub products. The aim of this paper is to propose a 5th level (i.e., level 4) to the UTMI+ specification by introducing a novel high speed serial interface (HSI), thereby making the UTMI+ transceiver to support all USB 2.0 products, including USB 2.0 hubs. The proposed interface will fill the gap that prevails in the USB transceiver industry between the USB 2.0 host/device and USB 2.0 hub transceivers. Ultimately, this proposal will make the UTMI+ specification a complete industry standard for all USB 2.0 products, thereby making the UTMI+ transceiver a true reusable component for all USB 2.0 products.

Keywords: USB2.0 Hub Repeater Latency Requirements, UTMI+ Specification Limitations, USB 2.0 Specification

The International Journal of Designed Objects, Volume 6, Issue 3, pp.73-91. Article: Print (Spiral Bound). Article: Electronic (PDF File; 4.502MB).

Sathish Kumar Ganesan

Electrical Design Engineer and Senior Staff, New Product Development Division, Cypress Semiconductor Technology India Pvt. Ltd., Bangalore, Karnataka, India

Sathish Kumar Ganesan: He is a Logic Design Engineer with 10+ years of experience in front end design activities with primary focus on Architecture, RTL design and Verification. He started his career in a Startup company whose primary focus was on USB2.0 IPs, where he designed USB1.x/2.0 Device controller with AHB, PCI, UTMI, UTMI+, OTG and ULPI inter-faces. He later moved to Samsung Electronics, South Korea, where he worked on WUSB MAC Controller Design, UWB baseband Design and Soc Verification. During this time, he worked as part of the Wimedia MPI Standard committee where his proposal for Low Power MAC-PHY Interface for PHY Register programming was accepted, standardized and released in WiMedia MPI Specification, Version 1.5. Then he moved to Cypress Semiconductor, India, where he developed USB2.0 Hub Controller Design. Currently, he is working in Cosmic Circuits Pvt. Ltd, Bangalore, India, where he is working on Connectivity IPs. His current interest is in Micro-Architecture, RTL design and other front end activities. Eventually he would like to work on system architecture. He is very interested in contributing new ideas for Standardization committees and wishes to work on innovating advanced new protocols that will help the consumer to make better use of technology.